Transient Analysis of VLSI Tree Interconnects based on Matrix Pade Type Approximation

This paper presents a novel, simple and accurate delay estimation model for single interconnect and tree interconnects, which is based on new matrix Pade-type approximant (MPTA). The proposed model provides a simpler rational function approximation for estimating delay and overshoot in lossy VLSI interconnects. Computational complexity is reduced by considering rational function denominator as scalar polynomial and avoiding matrix inversion. With the reduced order lossy interconnect transfer function, finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the existing Pade model and HSPICE W-element model. Single interconnect 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 1 mm long interconnects. For global lines of length more than 1 mm in SOC (system on chip) applications, the proposed model is found to be nearly two times more accurate than existing Pade model. Tree interconnects 50% delay values are also well agreeing with HSPICE and better than existing U-transform model. Furthermore the proposed model is computationally more efficient than HSPICE, Pade model and U-transform model. Key-Words: Delay, matrix rational model, ramp input, RLC interconnects, transient analysis, transfer function, Distributed tree interconnect, new MPTA approximant, U-transform.